In recent years, the semiconductor industry has realized tremendous advances in technology that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. Many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions on the single chip. Such devices include, for example, nonvolatile memory (NVM) memory devices and DRAMs (dynamic random access memory) which are composed of an array of memory cells for storing digital information. The peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers. Commercially, the drive for increased portability and continuous use while reducing size and weight of electronic hand-held devices has put more pressure on chip manufacturers to find ways to handle these requirements while reducing the chip size.
To improve performance and optimize these devices, it is very desirable in the electronics industry to provide FETs that have both thin and thick gate dielectric layers, usually oxide layers. A thin gate dielectric layer is used in the peripheral (logic) circuits to enhance FET device performance, while it is desirable to provide a thicker gate dielectric layer for the higher gate voltage requirements of analog and I/O circuits. For example, the FETs in the logic circuits would have a gate voltage of about 3.3 volts. On the other hand, the access transistor in analog and I/O circuits often require a significantly higher gate voltage.
A current approach to making these types of devices uses a grow-etch-grow process. In using the grow-etch-grow process to form the thick and thin gate oxides, the thick oxide layer is partially grown first. A photoresist mask is then provided over the thick gate layer region while etching the oxide from the thin gate regions; the entire wafer is then exposed to thin gate oxide growth. One drawback to this method, however, is that the photoresist mask contaminates the oxide and degrades the device's electrical characteristics. One such contaminant is the mobile sodium (Na) ion in the gate oxide that affects the long-term stability of the gate voltage on the is FET. Another drawback to this method is that it leads to higher defects in the oxide layer, as the initial thick gate oxide layer is exposed to the thin gate oxide preclean process. Attack of the thick gate oxide during the thin gate preclean process leads to formation of defects in the thick gate oxide.
There is a need to provide a method for forming the thin and thick gate oxides on a semiconductor substrate without the photoresist layer causing contamination of the gate oxide and without damaging the thick oxide layer during a thin gate preclean process.